CoaXPress™ Multi-Link Multi-Stream FPGA IP Core : DEVICE (Camera)

Device CoaXPress FPGA IP Core

Overview

The only CoaXPress FPGA IP Core supporting 6.25Gbps data rates, for both host and device sides, available on the market.
The CoaXPress IP Core from KAYA Instruments provides a Multi-link high performance solution for rate demanding video applications. Both Host and Device modes of operation are supported. The IP core offers support for newest and industry leading Artix 7, Kintex 7, Virtex 7 and Zinq 7000 FPGAs from Xilinx and Cyclone V, Arria V GX, Stratix IV and Stratix V FPGAs from Altera. The device IP core incorporates a friendly streaming interface with highly configurable pixel packer for glue less connection to imaging sensor or user logic.

Applications

  • High speed cameras
  • High definition cameras
  • Panoramic cameras
  • Existing coax systems upgrade
  • Defense remote systems
  • Slip Ring systems
  • Automotive surround view system
  • Surveillance
  • Robotic Vision

Features

  • Compliant with JIIA NIF-001-2010 CoaXPress standard rev 1.1
  • CXP-6 support of up to 6.25 Gbps high speed link and 20.83 Mbps low speed link
  • Multiple link rates support
  • Supports both Host and Device modes
  • Multiple CoaXPress links suited for applications demanding high throughput.
  • Multiple video stream support
  • Build in FPGA SerDes , no need for additional design effort
  • AXI4L/Avalon MM support for control channel
  • Highly configurable pixel packer
  • Host IP Core supports multiple device connection on different data rates
  • Embedded CRC-32 generate/check for streaming data packets
  • Avalon and AXI4 Stream Interface Profile in Host IP Core
  • Dedicated ports to for GPIO and trigger

Core Details

  • Single or multi-use license
  • Free license for KAYA Instruments CXP Mezzanine card users
  • Soft IP core: RTL-encrypted source code, synthesis scripts, etc.
  • Comprehensive documentation package
  • Support for Altera® and Xilinx® FPGAs
  • Language: Verilog HDL
  • Simulation environment: ModelSim

Deliverables

  • CoaXPress FPGA IP Core
  • Comprehensive usage Examples
  • Bootstrap register file with optional I2C/SPI IP Core

Gallery